The global semiconductor market is preparing for a significant architectural shift. Advanced Micro Devices (AMD) has officially submitted a patch package to the Linux kernel pool, introducing support for a fundamentally new type of compute core. This update marks the x86 industry's transition to a complex heterogeneous topology, similar to that used for many years in mobile ARM processors and the latest Intel solutions.

According to technical documentation published by the specialized resource Phoronix at the end of June 2026, future processors based on the Zen 6 microarchitecture will switch to a three-cluster scheme. While operating systems previously distinguished only between high-performance (Performance) and energy-efficient (Efficiency) cores, a third, independent category is now being introduced — Low Power.

Technical Implementation: How Linux Recognizes New Cores

AMD engineers have modified the x86/cpu/topology subsystem in the operating system kernel. Previously, Linux could only hardware-differentiate two types of cores: powerful cores for heavy tasks and compact cores (such as Zen 4c or Zen 5c) for everyday operations. The new update adds the AMD_CPU_TYPE_LOW_POWER classifier.

The identification mechanism is implemented via a call to the extended CPUID instruction function. The OS scheduler reads the core classification directly from the bits of the EBX register [31:28] when the function is called:

CPUID Leaf: 0x80000026 (Extended CPU Topology)

If the bit value equals 2, the system marks the logical core as belonging to the low-intensity cluster. This is critical for the correct operation of the task dispatcher, allowing it to distribute threads without glitches or conflicts.

A New Philosophy of Power Management

The emergence of a separate class of cores is dictated by the need to optimize performance in idle mode. As AMD developer engineer Vishal Badole noted, the new architecture is designed to serve background processes, system interrupts, and tasks executed in an idle state.

In such scenarios, the priority shifts from peak computing power to minimizing leakage currents and overall power consumption. The implementation of patches modifies dynamic frequency scaling algorithms. Dispatching for Low Power cores will rely on the feedback function amd_get_highest_perf(), allowing the scaling of operating frequency and voltage below the fixed base ceiling of standard energy-efficient cores.

Medusa Point Architecture and Physical Separation

According to analyst estimates, the physical placement of Low Power cores will likely be implemented on the input/output die (I/O die) in Medusa Point generation mobile processors. Such an architecture opens the possibility of completely powering down the main compute blocks (CCD) while performing light tasks: playing media files, checking network packets, or synchronizing data.

This solution is aimed at significantly improving the autonomy indicators of consumer electronics, which is a key factor in competition with energy-efficient ARM platforms.

Why This Matters for System Stability

Architectural division of labor requires advance software preparation. Without the integration of these patches into the Linux kernel, the operating system would identify the third type of core as "unknown." This would lead to critical thread scheduling errors and uncontrolled power consumption growth, negating the advantages of the new hardware architecture.