AMD Unveils 6th Gen EPYC Venice 9006: Up to 256 Zen 6 Cores, PCIe 6.0, and 31% IPC Gain in AI Workloads

AMD has officially unveiled its sixth-generation EPYC server processors, codenamed Venice (9006 series) — the most significant update to the lineup since the transition to a dedicated I/O die architecture during the EPYC 7002 Rome era. The new family combines the updated Zen 6 microarchitecture, a redesigned System-on-Chip (SoC), and PCIe 6.0 I/O subsystems. It covers a significantly wider range of tasks than its predecessors: from high-density compute nodes with 2 × 256 cores / 512 threads to energy-efficient systems using LPDDR5X memory. According to AMD, this is the most ambitious step in the evolution of the EPYC platform in several generations.

Zen 6 and Zen 6c Microarchitecture: Density vs. Frequency

At the heart of the EPYC 9006 are two nearly identical microarchitectures, Zen 6 and Zen 6c, which do not require special software optimization to work together but are aimed at different market segments. Zen 6c cores are optimized for maximum density: they occupy less chip area, lack 3D V-Cache support, and run at slightly lower clock speeds, allowing more compute blocks to be placed on a limited silicon area. "Classic" Zen 6 cores, conversely, are focused on achieving high frequencies. The flagship EPYC 9686F, initially announced with a 5.0 GHz peak clock, features a final specification of 5.3 GHz. Almost the entire SP7 socket lineup received a boost of approximately 100 MHz compared to preliminary specifications. AMD claims a 20% IPC gain over Zen 5, which, in corporate server workloads, may represent one of the most significant improvements in Zen history.

New AI Instructions: 31% IPC Gain

Particular attention in Zen 6 is given to expanding the Instruction Set Architecture (ISA) for artificial intelligence tasks. AMD has added additional AVX commands for INT8 processing, data format conversion instructions, and integer FMA operations — a technology previously pioneered by Intel. AVX blocks now feature full FP16 format support, allowing Zen 6 to execute intensive half-precision calculations as efficiently as FP32 and FP64 operations. The AVX-512 set includes a new command for bitwise matrix multiplication, accelerating specific bitwise matrix operations. Together, these improvements provide the claimed 31% IPC gain in AI workloads. Additionally, three new kernel-level virtualization instructions were added, including FRED (Flexible Return and Event Delivery), a new mechanism for transitioning between privilege levels. For developers, AMD has prepared instruction-based sampling buffering and a new memory profiler.

SP7 SoC Platform: PCIe 6.0, CXL 3.1, and Double Memory Bandwidth

The redesigned SoC architecture in the sixth-generation EPYC features several key updates reflected in the platform presentation. The I/O subsystem has transitioned to PCIe Gen 6, which doubles bandwidth per lane compared to PCIe 5.0. Memory bandwidth has increased by more than 2x — up to 2.6x improvement relative to the previous generation — while using standard (non-proprietary) JEDEC-spec DIMMs. Memory expansion is supported via CXL 3.1, and the SoC scheme includes CXL Memory and CXL Switch blocks integrated directly into the die. The platform supports 1P and 2P configurations with "G" and "P" links and provides a wide set of PCIe lanes per socket. Processor TDP (OPN) ranges from 400W to 600W, covering both high-performance and power-efficient deployment scenarios.

Lineup Segmentation: Venice-X, Verano, and Embedded Solutions

AMD has split the new family into several sub-families using two main types of sockets. The Venice-X models with increased cache are returning — featuring, according to sources, over 1 GB of L3 cache — and a Verano version with LPDDR5X support has been introduced for energy-efficient systems with broad I/O capabilities. The EPYC Embedded 9006 Venice series, according to insiders, will offer up to 96 Zen 6 cores with PCIe Gen 6 and DDR5/MRDIMM support on a 2nm TSMC process. Additionally, Embedded 4005 and EPYC Embedded Annapurna series are in development. Thus, the sixth generation of EPYC covers a much broader spectrum of tasks than before, representing, as AMD puts it, the most ambitious step for the EPYC platform since the move to separate I/O die architecture.

Developer Tools and Focus on Optimization

Alongside the new chips, AMD introduced a set of tools for developers looking to utilize Zen 6 capabilities effectively. These include instruction-based sampling buffering and a new memory profiler. The company emphasizes that a significant portion of the performance gain was achieved not through hardware scaling, but through optimizations that allow existing blocks to be loaded more effectively: micro-op cache has been increased, the instruction window expanded, and pipeline throughput improved. This approach, according to AMD, ensures higher IPC without a proportional increase in chip area or power consumption.