Tesla has taken a radical step in developing its hardware by significantly reducing the RAM capacity in its upcoming AI5 and AI6 artificial intelligence chips. Official statements from Elon Musk confirm that this move is driven by a global component shortage and the need to ensure stable mass production of processors for Full Self-Driving autopilot systems and humanoid Optimus robots.
Processor Architecture Characteristics and Changes
According to published data, the configuration of the AI5 chip has changed: the LPDDR5 memory capacity was reduced from 144 to 72 gigabytes. In turn, the yet-unreleased AI6 chip will receive 144 gigabytes of RAM instead of the previously expected 216 gigabytes. Despite the reduction in external memory, developers promise colossal computing power: AI5 is built on an advanced 2nm process node at TSMC and Samsung facilities in Texas and is expected to deliver between 2,000 and 2,500 TOPS.
The Role of On-Chip SRAM and Performance Impact
Tesla management assures that the reduction in DRAM volumes will not affect the ultimate capabilities of the humanoid Optimus robot or the autopilot system. Company engineers are compensating for the lack of RAM by significantly increasing the volume of built-in SRAM memory. According to Elon Musk, about half of the computational accelerator area in the AI6 and AI6.5 versions will be allocated to SRAM, providing unprecedentedly high data bus bandwidth.
Production Timelines and Market Prospects
Trial production of AI5 processors has already begun, though the market launch of final devices has been postponed. Mass production of AI5 chips is slated for 2027, while the full release of the next-generation AI6 is expected closer to mid-2028. Depending on the chosen configuration, Tesla expects to achieve a performance level comparable to NVIDIA's advanced solutions such as H100 and Blackwell, strengthening the company's leadership in robotics and autonomous transport.
