Taiwanese TSMC, the world's largest contract semiconductor manufacturer, is considering raising prices for advanced chip packaging using CoWoS technology by up to 20%, Taiwanese media report, citing TrendForce industry analytics and Commercial Times. According to their data, semiconductor manufacturers and outsourced semiconductor assembly and test (OSAT) companies are discussing price revisions in the range of 10% to 20%. CoWoS technology enables the integration of compute dies and HBM memory within a single package, making it critical for modern artificial intelligence accelerators. No official confirmation regarding a 20% packaging price increase has been issued by TSMC as of the time of publication.
AI Accelerator Demand Overloads Packaging
The growing demand for CoWoS packaging is driven not only by graphics processor manufacturers but also by server processor developers and specialized ASIC chip designers, who are increasingly adopting advanced multi-chip solutions. This is why capacity shortages are affecting multiple market segments simultaneously—from data center GPUs to custom AI accelerators—increasing price pressures across the entire supply chain. Analysts emphasize that supply is failing to keep pace with order growth, a classic scenario where price becomes a tool to balance demand and available production lines.
Testing Becomes a Bottleneck
An additional constraint is created by the increased testing time for finished processors. According to Nomura Securities estimates, testing Nvidia Blackwell accelerators takes four times longer than the previous Hopper generation, and for the next-generation Rubin, this figure could be seven times higher compared to Hopper. As a result, manufacturers require more testing equipment and lead times are extended, effectively reducing throughput even when dies and packaging are available.
Equipment Shortages and Abandonment of Traditional Discounts
Tensions have also affected semiconductor equipment suppliers, with delivery lead times for machinery increasing from the previous three to six months to six to eight months. According to Commercial Times, TSMC abandoned its usual practice of negotiating discounts and free functional expansions this year, placing orders at prevailing prices to avoid delaying the receipt of necessary equipment. This approach indicates that a persistent shortage has formed in the equipment market, where purchasing power takes a back seat to delivery speed priority.
Capacity Expansion and New Packaging Formats
To cope with the capacity shortage, TSMC is expanding packaging production. According to analyst estimates, its CoWoS capabilities should exceed 130,000 wafers per month in 2026 and reach 200,000 in 2027. The company has already mastered mass production of packages sized at five standard exposure fields and is developing solutions with nine- and fourteen-fold increases in this metric, which will allow placing more dies and memory modules in a single package and increasing the compute density of AI accelerators.
Readiness for Lithography Price Hikes
In parallel with packaging, TSMC is preparing to revise the cost of direct chip fabrication. According to Taiwanese media reports, starting January 2027, silicon wafer processing prices may increase by 3% to 6%, with the largest hikes expected for advanced 2nm and 3nm process nodes. Together, these steps indicate a systemic rise in the cost of advanced semiconductor products, which, following market logic, could spread to final AI accelerators and server equipment. For now, however, the 20% CoWoS packaging price increase remains an industry discussion topic and has not been confirmed by TSMC itself.
