What process node are Zen 6 and Zen 6c dies manufactured on?

On the TSMC N2P 2nm process node, which compared to N3E (Zen 5) delivers either +18% frequency at the same power consumption or −36% power consumption at the same speed.

How many cores does a single Zen 6 and Zen 6c die accommodate?

Standard Zen 6 CCD — up to 12 cores (48 MB L3), Zen 6c chiplet — up to 32 cores (128 MB L3).

How does Zen 6c differ from Intel's E-cores?

Zen 6c uses the exact same microarchitecture as Zen 6 and is an area-optimized variant of the standard core, whereas Intel E-cores are based on a separate architecture with limited instruction support.

What platforms support EPYC Venice and what are their differences?

SP7 — 16 memory channels, up to 1.6 TB/s per socket, up to 128 PCIe 6.0 lanes in 2P; SP8 — 8 memory channels, smaller dimensions, up to 192 PCIe 6.0 lanes in 2P. Both support CXL 3.1.

AMD Unveils Zen 6 Architecture: EPYC Venice Processors on TSMC 2nm Process Feature Up to 32 Cores Per Chiplet

AMD has published extensive technical details about the Zen 6 and Zen 6c architectures, which form the foundation of the sixth-generation EPYC 9006 Venice server processors. According to the company's positioning, the new chips are designed to directly compete with Nvidia Vera and Intel Granite Rapids-AP platforms. The first independent tests of the new processors were conducted by Tom's Hardware, while in a number of test scenarios, according to 3DNews review headlines, the new products showed results twice as high as the Zen 5 generation.

2nm Process and Core Density

Compute dies (CCDs) based on Zen 6 and Zen 6c architectures are manufactured using TSMC's advanced N2P 2nm process node. Compared to N3E, which was used in Zen 5, it delivers either an 18% frequency boost at the same power consumption or a 36% power reduction at the same speed. The Zen 6 design increased the number of cores per die by 50%: a standard CCD now accommodates up to 12 cores with 48 MB of L3 cache, while L3 cache access latency is maintained at 13 clock cycles, same as in Zen 5. A 27% geometric mean increase in IPC for AI tasks and server workloads is claimed, and the maximum frequency of Zen 6 processors has risen to 5.3 GHz compared to 5.0 GHz in Zen 5.

Energy-Efficient Zen 6c Cores

Chiplets based on energy-efficient Zen 6c cores claim the largest density leap: a single die accommodates up to 32 cores — twice as many as in Zen 5c. The L3 cache volume per core has been doubled (up to 4 MB), and the total cache volume per chiplet has quadrupled to 128 MB; maximum clock speed increased to 4.1 GHz compared to 3.7 GHz in Zen 5c. Importantly, Zen 6 and Zen 6c share the exact same microarchitecture inside the core: unlike Intel E-cores, which are based on a separate architecture and lack support for many P-core instructions, Zen 6c is an area-optimized design of the standard core with lower power consumption and lower frequencies.

Microarchitecture Changes

The new architectures introduce separate Integer Schedulers, and the physical register file has been expanded to 352 entries. The vector execution unit has received native support for FP16 half-precision instructions while maintaining full backward compatibility with AVX-512, and FP data load bandwidth has increased to two 512-bit or four 256-bit loads per cycle. The operation cache has been increased from 6k to 6.75k entries, and dispatch bandwidth from 12 to 18 operations per cycle.

SP7 and SP8 Platforms: Memory and PCIe

Zen 6 server processors for the SP7 socket feature two input/output dies (IODs) instead of one, located in the center of the chip, enabling support for 16-channel RAM. Operation with MRDIMM modules in 1DPC configuration at speeds up to 12,800 MT/s (with RDIMM up to 8,000 MT/s) is claimed, providing peak bandwidth of up to 1.6 TB/s per socket (up to 1 TB/s with RDIMM); up to 8 TB of memory can be installed per socket. SP7 also claims support for PCIe 6.0 with speeds up to 64 Gbps per lane: a single-socket configuration has 96 lanes, a dual-socket configuration has up to 128 lanes, plus 'bonus' PCIe 4.0 lanes (8 for 1P and 16 for 2P).

The SP8 socket has smaller dimensions — 62.5 × 80 mm — and supports eight memory channels instead of 16, maintaining MRDIMM operation up to 12,800 MT/s (bandwidth of 819 GB/s for MRDIMM and 512 GB/s for RDIMM). SP8 chips have access to 64 lanes of PCIe 6.0 per IOD (128 lanes total in the socket plus 8 PCIe 4.0 lanes), while dual-socket configurations provide up to 192 PCIe 6.0 lanes and 16 additional PCIe 4.0 lanes. Both platforms support the CXL 3.1 standard.

MEXT Technology and Supply Context

EPYC Venice will be the first platform to support hardware-software MEXT technology, which uses fast flash memory as a DRAM extension: using AI algorithms, the system predicts memory access and offloads unused pages. According to AMD, the technology provides advantages in critical design tasks. Amid the AI boom, the company is also ramping up production: AMD CEO Lisa Su, during a visit to Taiwan and South Korea, stated that the company has already increased shipments in 2026 and intends to significantly scale volumes in 2027, holding talks with Foxconn and TSMC.

AMD Unveils Zen 6 Architecture: EPYC Venice Processors on TSMC 2nm Process Feature Up to 32 Cores Per Chiplet