TSMC and NYCU Achieve Breakthrough in Microelectronics: New 2D Transistor Technology Based on MoS₂

In August 2026, the semiconductor industry received a powerful boost. Taiwan Semiconductor Manufacturing Company (TSMC), in collaboration with researchers from National Yang Ming Chiao Tung University (NYCU), unveiled an innovative technology that could become the foundation for next-generation chips. This development aims to overcome the physical limitations currently faced by modern processor manufacturing methods.

The Scaling Crisis and the Shift to 2D Materials

As of 2026, the industry stands on the brink of a critical juncture. Traditional FinFET and GAA (Gate-All-Around) transistors, which form the backbone of most modern processors, are reaching their physical limits. As the transistor channel length shrinks to just a few nanometers, the gate loses its ability to effectively control electron flow. Further reducing material thickness leads to a sharp increase in electrical resistance, making the classic silicon approach increasingly inefficient.

To address this challenge, researchers at TSMC and NYCU turned to two-dimensional materials. Special attention was paid to molybdenum disulfide (MoS₂). This material enables the creation of single-layer transistors with a thickness of only about 0.7 nanometers. Thanks to this structure, MoS₂ provides superior current control and paves the way for significantly increasing transistor density on a chip, which is crucial for future computing power.

Innovative Interface Formation Method

The main obstacle to implementing MoS₂-based transistors was the difficulty of creating a high-quality gate dielectric. Traditional methods of depositing materials onto the transistor channel resulted in uneven surface coverage, reducing chip performance and reliability. The TSMC and NYCU team proposed a revolutionary approach that completely changes the sequence of the technological process.

Instead of directly applying insulation to the channel, engineers first modify its surface. They deposit an ultra-thin epitaxial layer of aluminum, which is then oxidized to form an aluminum oxide layer just 0.42 nanometers thick. It is this ultra-thin intermediate layer that becomes the key to success. A high-k hafnium oxide dielectric layer is then formed on top of it. This multi-layered "sandwich" allows for the creation of an ideal boundary between the channel and the gate.

Results and Prospects for Mass Production

According to researchers, the new technology significantly reduces electron scattering and minimizes defects at the material interface. This directly impacts the energy efficiency and speed of future chips. If the technology proves its stability and effectiveness in mass production conditions, it will become one of the key foundations for creating processors with processes that go beyond current standards.

The success of this development is also important in the context of global competition. In a situation where chip manufacturing costs are rising (as reported in forecasts for 2027), the ability to create denser and more efficient transistors gives TSMC a strategic advantage, allowing it to offer clients a better price-to-performance ratio.

Contradictory Data

While the technical aspect of the development looks convincing, there are nuances in assessing the implementation timeline. On the one hand, researchers claim the technology is ready for integration. On the other hand, market experts point out that the transition from laboratory samples to industrial production on 300mm wafers could take several years. Furthermore, some analysts note that in 2026, the industry is still actively mastering current generations of GAA transistors, and a premature shift to 2D materials could face economic barriers despite technical readiness.